Design And Implementation Of High Speed Mpsk/mqam Signal Demodulation Algorithm Based On Fpga

This thesis focuses on the design and implementation of real-time demodulation of high-speed MPSK/MQAM signals based on FPGA including digital down-conversion, re-sampling, fractionally-spaced equalization and synchronization etc. The work finished in this paper is a part of the overall task targeting at a key project undertaken by our laboratory.The main work and achievements of this paper are summarized as follows:1. According to the features of high speed signal and the requirements of FPGA implementation, the demodulation algorithms of high speed signal is designed and implemented, which mainly contains the design of hign speed digital down-conversion and synchronization.2. A kind of NCO structure for digital down conversion based on the combination of multiplier and looking-table is implemented which uses less multipliers and memory, thus can save a lot of resources of FPGA. A five-stage CIC filter with high decimation factor is used which uses less logical resources while obtains better decimation-filtering effect. A FIR filter based on distributing algorithm is used for high-speed filtering without the use of multipliers.3. In order to cope with the very high data stream after interpolation, a high-speed resampling method based on multi-phase structure is proposed, which can greatly reduce the throughput after interpolation, thus is much easier to implement. Due to direct decimation after multiphase interpolation, the structure can be simplified to only contain a FIR filter plus a simple scheduling control unit.4. A new modified fractionally-spaced blind equalizer is proposed, which uses a timing algorithm to replace the pure decimator unit contained in conventional structure. As a result the new algorithm possesses both equalization and timing correction functions.The inversing filter in the front of the synchronizing algorithm can prevent the algorithm from the channel aberration.In order to achieve better equalization,the CMA and dual-mode algorithms are used for MPSK and MQAM signals respectively.5. In consideration of limited FPGA resources, Gardner PLL-based timing and carrier synchronization algorithm based on decision making are adopted and implemented. Both of which are simple and suitable for FPGA implementation. A decision-aided algorithm is implemented for carrier synchronization, which can meet the basic need of carrier tracking while requiring less resources. Classical AGC structure with lager dynamic range is adopted. Both quick-adjustment and high accuracy are achieved for two different processing units respectively.Finally, all the above functional algorithms are incorporated into a whole system which is optimized in terms of resources, speed and accuracy. A comprehensive debugging is completed. Test results targeting at both signals generated by the E82670 signal generator and real satellite signals available in the laboratory are provided,which have proved the feasibility and performance improvements of the real-time demodulation system for high-speed signals.