A Study Of The Matrix Operation Harden Implementation On Fpga

Matrix operations are widely used in scientific computing, digital signals processing and image processing. These applications call for run-time. Therefore, it is useful to implement the matrix algorithms for high speed. FPGAs can provide both high parallel and better flexibility than ASIC and GPP and has achieved significant speedups in many applications. This dissertation discusses how to implement the matrix multiplication, matrix decomposition and matrix inverse on FPGA.The thesis first describs the design principle of the floating-point operations and the realization method of the basic floating-point operation uinits on FPGA, analyses the lower bound on the cycle of matrix multiplication and ascertains the prime parameter during the architecture design. And then, the thesis analyses the linear array architecture of matrix multiplication and the circular linear array architecture of matrix decomposition, makes an improvement and optimization on these two architectures, proposes a new architcrure for implementing matrix inverse on FPGA, gives the configurations of the processing element for each architcrure and the schedule of the three matrix operations, design and implement the matrix multiplication, matrix decomposition and matrix inverse on FPGA.Finally, the thesis tests on the executing time and the floating-point performance of the three matrix operations. It comes out that the floating-point performance of our design is 4~90 times higher than Intel Pentium 4 3.0GHz CPU and 1.6~2.5 times higher the linear array and circular linear array architecture.