The Research And Implementation Of Security Vulnerability Detection Platform On Pld

Security vulnerability detection of the integrated circuit has been presented in order to discover the chip defects, clear the hardware backdoor attacks, maintain the electronic equipment, and promote the design capability of integrated circuit of our country. Meanwhile, it is an effective way to protect the information security in the basic level.Taking the research on "863"goal-oriented subject as background, this thesis studies on PLD which is widely used in the present digital circuit equipment, and mainly focus on its discrimination of the external attribute of Logic-unknown devices, the detection of logic security vulnerability, the visual display of security vulnerability. Furthermore, this thesis designs and realizes the PLD security vulnerability detection platform based on the research achievements. On the basis of the detection platform, systematic measurements are conducted on all kinds of potential security vulnerability of PLD chip, and the test results indicate that the expected goals are achieved.Major contributions and innovations endeavored in this thesis are as follows:1. Logic device vulnerability detection model is constructed by analyzing the interior structure of PLD, the existing forms and the operation principles of security vulnerability of PLD. This thesis discusses the approach of security vulnerability detection on PLD, and presents the key problem which needs resolving in the process of the detection.2. Aiming at the key problem which would affect the time complexity and accuracy of attribute discrimination, the thesis proposes the idea of classification discriminance on clock pin and enable pin. This idea optimizes the existent synchronous discriminance on the chip's external attribute, and improves the efficiency of discriminance and accuracy enormously.3. According to the characteristic of the PLD security vulnerability, the thesis proposes an approach of off-line state stimulation detection and on-line state contrast to realize the security vulnerability label. Moreover, the thesis implements the unchecked chips'display of the state transfer map and state attribute with the visual technology based on diagram.4. Based on the PC architecture, the thesis designs and builds a PLD security detection platform. On the basis of the platform, real chips are tested and test results prove the vulnerability detection technology which is discussed in the thesis is correct and effective.