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Power Device Package Failure Analysis Techniques And Technology Research

Posted on:2009-01-17Degree:MasterType:Thesis
Country:ChinaCandidate:D H WuFull Text:PDF
GTID:2192360272959001Subject:Materials science
Abstract/Summary:PDF Full Text Request
With the increase of working voltage/current and the decrease of the chip size, the internal electric field of power MOSFET rapidly increased. All those factors constitute a challenge to the reliability of power MOSFET. Improving the reliability of power MOSFET has attracted more and more attention. Finding out the failure mechanism by failure analysis and then improving the packaging process and material is an effective approach to improve the reliability of device.PEM system is an effective tool widely used in leakage localization and analysis of microelectronic device. OBIRCH (Optical Beam Induced Resistance Change) function and EMMI (Emission Microscope) function of PEM are applied to locate and observe the strong leakage of power device from the front-side. EMMI function also can be applied to locate and analyze the weak leakage of power device from the backside. Application of PEM system in localization and analysis of leakage of different levels of power device also was introduced, thus provide a reliable evidence for leakage failure analysis of power device.To investigate the influence of electrical overstress (EOS) on reliability of power MOSFET, failure analysis was employed to research the reliability of devices including defects of solder void, gate open and die crack, respectively. After using finite element analysis, circuit simulation and reliability accelerated test, the root cause of EOS was confirmed. EOS resistance of devices after optimizing die attach temperature-time curve was compared using Unclamped Inductive Loading (UIL) test with that of before in this paper. It is found that the volume of solder void is observably decreased and EOS resistance is obviously improved after optimization.Wire bonding is the most important process in semiconductor packaging industry, that's because kinds of failure are related to this process. Crack and void exist in Al layer of chip surface weaken the reliability of power MOSFET after wire bonding was researched in this paper. By measure the thickness of Al layer and grain size and hardness, Al void and intermetallic compound affect the wire bonding quality was study. It's an important significance to analyze the stress distribution in substrate by finite element analysis, which will help to control and optimize the wire bonding parameter and improve the reliability of power MOSFET.
Keywords/Search Tags:power MOSFET, leakage localization, electrical overstress, wire bonding, failure analysis, process optimization
PDF Full Text Request
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