Capless Ldo Used In The Soc Design And Realization

With the development of the portable electronics towards smaller, more powerful function, SoC(System on Chip) become the direction of integrated circuits'development. Linear Regulators for that its external application is simple, the low output ripple and low noise, low cost, high power supply rejection ratio, etc. more easily integrated into SoC systems. Cap-Less LDO is easier than the traditional integrated in SoC. But there are larger defects in the transient response and stability of Cap-Less LDO. In order to improve the system of standby time, the static power consumption of the proposed LDO is limited, the transient response and stability of Cap-Less LDO become more challenging in this condition, and therefore design a good transient response Cap-Less LDO with low power consumption become a hot research and focus.In this paper: first, the basic operating principle of LDO was introduced, derived the formula of line regulation, load regulation and power supply rejection ratio and pointed out that trade-off relationship between them. Analysis of the process of the traditional LDO's transient response and all the factors that affect the transient response, the process of the LDO with capacitance or without capacitance are compared. A novel transient enhancement technique based on Voltage-Spike Detection is proposed. The circuit mainly include sampling capacitance, an improved current mirror and the current comparator, the static power consumption happen only when the output voltage change, But it boost the slew rate and improve LDO's transient response. All-in-one regulator with Voltage-Spike Detection have many drawbacks, A novel LDO with low static power, higher robustness is proposed based on it. Finally, based on the above study, in 0.13um CMOS technology, a transient- enhanced cap-less LDO which is used in mobile phones is designed. The process of design, datasheet and transistor-level schematic is showed. The simulation result shows that the overshoot the output voltage of LDO without any capacitance, the static power consumption of 15uA, the dropout-voltage of 300mV are less than 200mV when the load stepping between 0 and 100-mA in 1us. Compared to LDO without SRE, the overshoot voltage is decreased 150mV. Finally, tape-out, packaging, testing, simulation results is verified.