Configurable Hardware Design For Acquisition Of GPS/Compass Receiver

With the rapid development of GNSS (Global Navigation SatelliteSystem) technology, the application of satellite navigation system hasgradually covered all fields such as daily life, transportation, and mapping.However, the extensive usage of GNSS technology also brings challengesto the design of GNSS receivers. The challenges come mainly in two ways:to process GNSS signal in a short time to get high positioning result, andto reduce the power consumption of GNSS receiver which is usuallybattery-powered.There has been a lot of research on algorithm and design of GNSSreceiver. Early research mainly focuses on the USA’s GPS system (GlobalPositioning System). As the Beidou/Compass Navigation Satellite Systemin China has been developed rapidly during these years, navigation systemwith Compass has become hot research topic. While GPS/Beidou jointnavigation is providing better positioning performance, low power and lowcost receiver design is needed to promote the usage of Compass.The acquisition module of dual-mode GPS/Compass receiver is set asresearch objective in this thesis, and it’s designed by taking variousalgorithms and hardware details into consideration. Then the design isimplemented, optimized and evaluated. The main content of this paperincludes:(1) The method of the circuit reuse of GPS signal processing andCompass signal processing is assessed by comparing the signal structure ofGPS and Compass.(2) Acquisition algorithms are compared in the perspective ofcomplexity and flexibility. Then hardware architecture for acquisition is designed based on the Doppler parallel acquisition algorithm andimplemented using Verilog.(3) Then the design is optimized in three parts: sensitivity, hardwarelogic resource and memory resource.