The Research And Realization Of Neural Network Based On FPGA-K-means Clustering Algorithm

Resent years, neural network gets more and more widely apply, meanwhile people research on the neural network deeper and deeper. RBF neural network is a kind of typical neural network. It has the simple structure, training for it is pithy, and also the rapid study constringency, it applies at analysis of time series, model recognition, un-linear control and imagine processing and so on. The representational studying algorithm-K means clustering algorithm is kind of typical studying algorithm for researching RBF neural network. Researching the algorithm has done very well by software, so the issue accelerates this algorithm by hardware at the basis of the researching by software.FPGA (Field Programmable Gate Array) is a programmable digital integrate circuit IC (Integrate Circuit), According to the advantage by itself, recently, it gets widely researching both at home and at abroad. Its structure is very flexible and this character makes it more be fit for using of pipeline structure and plenty of registers. FPGA can be used to implement any design of hardware and also add software to processor, especially the application which requires process inputting dataflow rapidly. we analysis the algorithm by 2 ways, one of all by software, the other by hardware, the former has been researched by so many people, furthermore they acquired plenty of production, but limited by the complex process of software implementation. We can't accelerate it by ameliorating on algorithm, so we figure it out to implementing algorithm by hardware, to achieving make the algorithm to be accelerated.This paper start from analyzing the characteristic of algorithm, first of all, the above conditions is necessary for be propitious to implementing by hardware, namely requiring process input data flow rapidly, and also with parallel, furthermore the characteristic of K-means clustering algorithm accords with the characteristic of FPGA, software implement the data one by one and cycle N times, till the end of implementation, we completely parallel implement data, if we implement K-means clustering algorithm by FPGA, then K-means clustering algorithm can increase speed and improve efficiency in a large degree, while the algorithm get accelerate, it's more helpful for researching RBF neural network. The paper in Chapter IV described in detail how to achieve K-means clustering algorithm, we use a kind of design of top-down design, and we apply a classical principle of the FSM in the design of the module, the paper make simulation test and the logic synthesis for the total module and some important small module, The whole design prepared under Xilinx's ISE environment, at the end of the paper, we compared the result of the simulation test with the result where we got it from software. Finally, we talked about the future work.