Design Of System Clock For Wireless Sensor Networks

As a new generation of sensor networks, Wireless Sensor Networks (WSN) has various applications in many fields. The WSN system on chip, of great importance, is the ground of WSN. Its complicated applications make the power supply hard to replace. Therefore, low power consumption and high performance clock system are very important to the wireless sensor networks. As times develops, system clock source has developed from single outside output to both inside and outside output.In this thesis, an optional power mode and multi-sources clock system was designed for a wireless sensor networks chip which is based on the analyses of domestic and overseas papers about multi-clock system, crystal oscillator and RC oscillator. The primary works are listed as below: designed an optional power mode multi-clock system which turns off some parts in chip so as to realize low power consumption; designed a 32 MHz crystal oscillator which provides precise clock signal in full-speed mode; designed a 32.768 KHz crystal oscillator with amplitude control which provides slow clock signal with low power consumption; designed a 16 MHz inside RC oscillator which starts up system clock quickly; Designed a 32.768 KHz RC oscillator which uses a 70 nA current source from LDO so as to keep frequency stable.The design is based on the HuaHong NEC 0.25μm CMOS process. The simulation results obtained show that the functions and performances of this multi-source clock system meet the spec well. And it reduces the system power consumption successifully by dynamic clock management.