Chaos-based Encryption Algorithm Neural Network Security Chip Design And Its Application In The Application Of E-commerce

As the rapid development of information technology, the risk of its safety for real-time communication arises. Because of the unavoidable deficiencies of the original software encryption scheme, people pay more and more attention to the hardware encryption technique. And more and more people attach great importance to the research of security chip with higher safety which can process information fast. Neural networks can implement fast parallel computation; meanwhile it has the characteristic of complex chaotic dynamical process, so it is one of the best choices to assist security chip design.In this paper, we first introduce the parallel computation principle and chaotic characteristics of neural networks. The neural networks not only has a real-time parallel processing ability, but also a system with high level computational complexity. Second, we will introduce the basic principle of the symmetrical block encryption scheme based on the chaotic series and the unsymmetrical block encryption based on the chaotic attractor to analyze the security nature of these two schemes.According the architecture of Trusted Computing Platform, the parallel computation principle and chaotic characteristic based on neural network, and the characteristic of FPGA, we design two kinds of encryption scheme security chip based on the study mentioned above.(1) The secure chip of symmetrical block encryption/decryption algorithm based on Aihara chaotic neural networks which designed with FPGA. This paper analyzes especially the binary sequence output by Aihara chaotic neural network which designed with FPGA. And the analyze result indicates that this sequence is chaotic.(2) The secure chip of asymmetrical block encryption/decryption algorithm based on chaotic attractor of the Hopfied's neural networks which designed with FPGA. This paper attains especially fast processing of generating and classification of chaotic attractor.In this paper, the block diagrams of secure chip whih applicable to the Trusted Computing is presented, and the design procession and operation principle of the Trusted Computing modularity are also described. At last, these chips of encryption algorithm with FPGA are simulated and tested. The result indicates that the FPGA implementation schemes of these two kinds of chips are feasible, with high security and satisfactory encryption speed.In the end of the paper, a mixed encryption system which is designed for transporting the electronic commerce data safely is introduced. The block structure and operation principle of the system are presented, the security and encrypt speed are also analyzed.