On QoS-Guaranteed Switching Swcheduling

In recent years, real time applications such as IPTV and video on demand are growing rapidly. These real-time applications require the network supports guaranteed Quality of Service (QoS) parameters (including end-to-end delay and jitter of delay). Jitter measures the variability of delay of packets in the stream, which is an important property for real time applications. Lower jitter means smaller buffer size at the destination end. Keeping the jitter under control can also make the network more manageable. We first foucus on the problem of low jitter scheduling algorithm. We introduce the redundancy problem in the greedy low jitter scheduling heuristic. Then we propose Integer Average Redudancy Control and Dichotomy Sequence Redundancy Control to alleviate the jitter brought by redudance. We prove the upper jitter bound of both redundancy contol schemes are lower than that of no redundancy control case. By simulations we demonstrate that the jitter performace is apparently improved after redundancy controlling. We also make use of properties of Dicotomy Sequence to lower the complexity of redundancy control scheme.One important way of improving the performance of network is increasing the bandwidth of switch. For single-stage switch, the speed is limited by the central scheduler. The Load-balanced switch architecture is considered as one of the most promising high speed switch architecture because it has no scheduler and is amenable to optics. One problem of load-balanced architecture is mis-sequencing. First we propose a scheme called Dynamic Mailbox Sharing (DMS) to solve the mis-sequencing problem in the output port. The DMS Scheme is based on two statistic character of real internet traffic: the number of simultaneous active flows is in hundreads; the intra-flow packets interval is usually larger than its delay in switch. We lower the complexity of mailbox by dynamic sharing mechanism, which makes the requencing by flow feasible. By simulations with input of real internet trace, we demonstrate that the delay of DMS scheme outperforms previous schemes and is very close to the ideal case without re-sequencing. Second we propose a scheme to solve the mis-sequencing problem in the input port. We pove that by adding a simple path distributor in the input port, we can get an upper bound of the interval of out-of-sequenced packets. We use reshaper to constraint the intra-flow packet interval in the no-resequencing region. Then we get a very simple sheme with reshaper and path distributor to solve the resequencing problem in the load-balanced switch.