Test Data Generation Based On Evolutionary Testing And Data Compression In HDL Circuit

The integrated circuit dimension and the density of integration have been expanding, which lead to the test vecotrs needed by the test circuit to increase greatly. The important problem we must face now is that how to make the circuit to achieve the anticipant test result under limited time and source condition. The integrated circuit design has been becoming more and more sophisticated and using hardware description language to design complex integrated circuit has also been a tendency. Considering from the development of EDA technology, using the C language to design CPLD/FPGA will be the progress direction. There have been many mature test data generation methods in software test and measurement. To introduce the software test method to the test of circuit which is designed by the hardware description language can get better results.The paper presents to build test platform by using modelsim programmable language interface. The C/C++ programe and the Verilog hardware description language can transfer each other. And apply the test data generation methods in software test to the circuit test improve the Evolutionary Testing algorithm, create the test data. Modifying the sequence oder and abandoning irrespective test vector to make the test vector converge. Promote the data compress algorithm and finally improve the test efficiency. Experiment result proves that this algorithm has more effectivity than others.