Estimation Of Common-Mode Noise With FPGA

In a digital common-mode noise attenuation system for switching power converters,one of the key issues is the estimation of common-mode noise. Because the oscillation frequency of the current bringing commom-mode noise is very high, it is very difficult to achieve high-speed data sampling for the DSP device. This article proposed the technology of estimation common-mode noise with the energy of switching cycle and FPGA as the main component. In the plan mentioned, FPGA can carry out controlling of high-speed A/D converter, reading of the sampled data, and computation energy values of commom-mode noise, and sending these values to DSP.The main contents are made up of the following: common-mode transformer design, hardware design, FPGA function design, and the configuration and debugging of FPGA.The common-mode transformer design is primary to sample common-mode current signal. After common-mode transformer transform the common-mode current of main circuit to voltage signal, analog-digital conversion and common-mode signal sampling can be carried out. The design and manufacture of common-mode transformer is one of the key elements of common-mode noise detection. I use the general principles and formula of magnetic components to finish designing of the common-mode transformer in this paper.Hardware circuit design contains the design of the circuit board and the choice of FPGA device: MAX1448 is choosed a/d chip of the system and EP1C3T144C8 is choosed FPGA device.We need consider a number of problems of designing of high-speed signal circuit in designing circuit boards.We use the method of a bottom-up design to achieve of designing FPGA: the overall function module is divided into a number of sub-modules,and each of sub-modules complete some relative simple function; Then every sub-module is designed to complete the specific tasks; Finally the roof module is designed, so that the whole system could eventually finish the overall function.In this system, the FPGA configuration mode is the following:in debugging stage, JTAG way configuration is used and in stable operation stage, AS way configuration is used.debugging of FPGA is made up of high-speed data sampling,debugging of communication between DSP and FPGA, and ultimate debugging of the whole system. Finally, I analyse simply the error of the common-mode noise.