A Parallel Platform For Swarm Intelligent Algorithm's High Performance Computing

Intelligent Computation is a new important research direction of artificial intelligence research that has been given broad attention in recent years; it is also a main part of intelligent information processing as well. As an optimization algorithm based on the theory of biologic evolution, the most outstanding advantage of Intelligent Computation is its strong global optimizing capability and fewer parameter as compared with other optimization algorithms. QPSO is global convergent and will be a promising solver for complex optimization problem, which is shown by some previous work. Thus, the research of this paper will be of somewhat significance in intelligent computation area.In this paper, the design of the hardware is firstly formulated, and in turn the ant colony optimization algorithm, the PSO and QPSO, then compared them. On this point ,I proposed an improved approach which can use EDA technologies to realize the QPSO algorithm, and designed a high-performance hardware platform in modular. Although fewer number of parameters, but QPSO algorithm also is very complicated. To enable the system to complete the complex operation, the hardware platform used the micro-programming alternatives to the traditional state machine to compile control module. Between modules, using parallel technology to speed up the high-performance computing platform. The clock network uses the global clock network replace the original counter, which strengthens the drive. Effectively eliminating the timing disorder, but also provide special hardware support for the characteristics of the algorithm. Because FPGA can be modified as software, although it is hardware in nature, which can be maintained and updated easier, the technology have been chiefly chosen in numeric system design now.Finally, the paper proposes architecture of the hardware computing platform, use hardware language VHDL (Very High Speed Integrated Circuit Hardware Description Language) describe all the models, and gets the simulation. It is tested in the platform of Xilinx Spartan 3 and got the partial simulation, which indicates this patform could work in the low cost FPGA. This research demonstrates that a hardware implementation of the QPSO results in a small design for resource-constrained devices, and for its high execution efficiency, low power consumption. Greatly increase the practical value of the QPSO algorithm.