Study And Design Of CMOS Current-Steering Digital-to-Analog Converters

With the rapid development of integrated circuit (IC) technology, digital to analog converter (DAC), as an important interface component, improves greatly both in resolution and sampling rate. However, for the trend of very large scale integration (VLSI) and system on a chip (SOC), low power and fab process compatibility are more and more importance.A 12-bit 26-MSample/s low-power current-steering CMOS DAC, focused on GSM (Global System for Mobile Communication) transceiver, is presented. DAC based on current-steering architecture provides good matching among current sources, such that high resolution is possible. Besides, DAC with very high output impedance can drive resistance load, so it can realize very high sampling speed.The DAC, is designed with the top-down methodology. According to the application requirement of transceiver, the specifications of DAC are decided. Matlab is used to compare binary-weighted DAC with thermometer-coded DAC. Considering the performance and area, the segmented architecture of '8+4' is chosen, that is, the number of bits in the MSB and LSB is eight and four respectively. Subsequently, Verilog-A and Verilog are used for behavior level design and blocks specification. In the circuit design, the blocks such as register, decoder, current cells decoding logic, bandgap voltage reference, voltage-to-current converter circuit, current source and differential switch are analyzed. For the optimized structure of the system, relatively low power consumption and area are realized.The DAC is implemented using TSMC 0.18μm Mixed CMOS process, and the simulator is Spectre of Cadence. The result of differential nonlinearity (DNL) and integral nonlinearity (INL) are better than±0.2 LSB and±0.25 LSB. A spurious-free dynamic range (SFDR) is about 83dB, when an input signal is about 200 kHz at 26M clock frequency. It dissipates 20mW from 3.0V analog voltage supply and 1.8V digital voltage supply.