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Design And Implementation Of H.264 Video Encoder On TMS320C6711

Posted on:2009-01-22Degree:MasterType:Thesis
Country:ChinaCandidate:Y LiuFull Text:PDF
GTID:2178360272483288Subject:Traffic Information Engineering & Control
Abstract/Summary:PDF Full Text Request
With the improvement of network and communications, the compression of multimedia video has been becoming more and more popular in a variety of fields, such as video conference, video phone and so on. The latest video coding standard H.264/AVC is used widely because of the good coding capability. But its algorithm is so complex that its coding speed is slow. Then, the application of H.264 is limited in the real time system. On the other hand, it is necessary that use the embedded system in place of PC to reduce the cost of the system. Thus, an efficient embedded video compression system of H.264 is not only significant to the academia, but also helpful to the industry.This thesis develops a real-time video compress system based on H.264 standard on DSP platform. But, when the original H.264 codes run on the DSP platform to dispose the video, the system isn't real-time. Some problems such as the code is too long, the space of the memory is small and so on affect the coding speed. To solve these problems, the thesis finishes the following works:1. When designing the hardware of the system, the DSP which meets the demand of the task is chosen. The platform of the hardware is build. The hardware consists of a video camera, a TMS320C6711 DSP simulation board and a display. The function of the hardware is collecting the video, coding the image and displaying it.2. When designing the software of the system, the algorithm code which wastes the more time of H.264 is redesigned. The codes of the method of selection in intra prediction mode and the searching approach of the motion estimation are rewritten.3. After transplanting the code on the TMS320C6711 hardware platform, the memory is distributed according to the inside structure of C6711 chip reasonably. In this course, the space of L2 and the data of SRAM is configured, Cache is optimized.When the data is moved between the interior RAM and the exterior SDRAM, the bottle-neck problem between the fast CPU and the slow SDRAM is settled by introducing EDMA mechanism.4. According to the analytic result of profile of CCS, the section of the C code which consumes a lot of time is rewritten.The experiment is done, and the video catched by the camera is coded. The interval of the I frame is 10 frames. The coding time of one I frame was 27.3ms, and the coding time of one P frame was 51.0ms. The average frame rate was 20.55 frames per second. This satisfied the demand of a real-time video system liked the video conference, and the quality of the decoded video is good.
Keywords/Search Tags:H.264, DSP, video coding, optimization
PDF Full Text Request
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