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Research Of LDPC Encoder Based On Improved Semi-random Matrix

Posted on:2008-09-23Degree:MasterType:Thesis
Country:ChinaCandidate:F XuFull Text:PDF
GTID:2178360272467459Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Low density parity check (LDPC) codes have received major attention in the research community in recent years because of its excellent error correction capability and performance. Great progresses have been obtained in LDPC algorithm in recent 8 years, however there are many Inadequate aspects, for there is no a perfect program which can meet the performance,complexity and the cost of hardware implementation.On the aspect of method of code construction, the thesis presents a method integrated advantages of some aspects. firstly , In order to accommodate different code parameters and low complexity , the parity check matrix is based on the semi-random matrix ; and then , expanding measures based on base matrix is used to avoiding the 4-girth when code length is long ; lastly , the thesis choose the appropriate value for the expanding shift factor by the relationship of the girth,expanding factor and shift factor, which can enhance the performance of LDPC code .On the aspect of method of hardware implementation, the thesis present a new method to store the parity matrix based on the matrix's characteristic, which occupiers little memory.Through the result of simulation on the matlab ,the algorithm can effectively eliminate the girth-aggregation-effect .The performance of new LDPC code is more robust, and it can obtain approximate 0.4dB coding gain in the region of BER < 10?5dB.What's more ,under the different code rate , performance is still robust.The result of function simulation on modelsim is the same as matlab. The delay of encoding is about 35μs which is under the condition that code length is 4096 , code rate is 1/2. It shows little delay .With the device spartan3 XC3S400 , the results of synthesizing shows it occupies 3876(54%) LUTs ,the operation frequency is 81.5MHz.the encoder has a low hardware complexity.
Keywords/Search Tags:FEC, LDPC, Dual-diagonal-quare-matrix, girth
PDF Full Text Request
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