FPGA Implementation For Alarm System And Multi Targets Detection And Tracking In Infrared Image

With the rapid development of science and technology, IRFPA(infrared focal plane array)detector has come into being. The appearance of IRFPA detector is an epoch-making revolution in the history of infrared imaging. Meanwhile, infrared imaging system is widely used in both civil fields and military fields because of its good performance. First, we introduce an interface design on 288×4 Element Linear Infrared Focal Plane Array. And then we discuss some of the key technology of the small target detection in infrared image sequences. At the end of the paper, we introduce a design using FPGA as coprocessor for DSP to process image information.The detection of small target in infrared image sequences includes three main procedures: preprocessing, region labeling and multi-frame accumulation.This paper first illustrate the features of infrared images and the basic principles in the detection of small target in infrared images, after that the way that how the preprocessing of image and the labeling of target are done is introduced.Spatial filters are used in preprocessing and the hardware structure of a 2-D window operator is introduced; Then a meadian filter and the gray-scale morphological erosion and dilation operation based on this structure are presented. An new hardware implementation of morphological filer using pipeling is presented to improve the system performance. Also we use an variable 1-D structuring element to replace the 2-D structuring element because of the disadvantages of the 2-D structuring element morphological filter.Two methods are introduced in region labeling:One is based on segmentation. The other one is based on the sort of target gray;A candidate target list is created and updated with the compare of gray and neighbourhood. The hardware implementation of both methods are presented.According to DMA function, I first design DMA behavior level and detach it to clock-driver cell which can separately control signal from data signal, and design structure which consists of control block, data channels and address channels.