FD SOIMOS Device Simulation-Submicro FD SOIMOSFET Threshold Model And New Structure Device Research

Silicon-On-Insulator (SOI) CMOS circuits have been widely used in the field of low-power and high performance ICs. due to its advantages in lower junction-capacitance, smaller second order effects and latch-up immunity.Since CMOS integration technology has play an important role in the field of VLSI, and the universal implementation of EDA (Electron Design Automation) tools , the compact modeling of SOI MOSFET always become one of the concerns of research and as a bridge between EDA and TCAD (Technology Computer Aided Design).As the device scaling down to deep-sub-micrometer, small size effects have brought new challenges abouts the SOI devices. On the one hand, the compact modeling of SOI device should take short channel effects(SCE) and floating body effects into consideration. On the other hand, in order to achieve the characteristics of the device to the smaller size of the node into the technology, performances and gate control capabilities of SOI devices could be improved from structures and materials. And the devices structure should be developed from 2D to 3D.In this paper, some new opinion about the compact model and SOI architecture against SCE is presented. Based on the introduction of SOI history and fabrication, a new threshold voltage model is proposed for fully depleted SOI MOSFET with asymmetric HALO. Threshold voltage model reflects the two-dimensional effects in both SOI and buried-oxide layer. The predictions of the model are in good agreement with the two-dimension numerical simulation by MEDICI. Compared to the one-dimensional model, two-dimension effects in the buried-oxide layer of the deep submicron MOSFET device create the SCE more quickly. In chapter 4, the development of SOI device structure is introduced. a novel structure called MGate-SOIMOSFET is proposed. In chapter 5, Characteristic of MGate-SOI MOSFET is researched by three-Dimension simulator DAVINCI. The expectation about the compact model and structure of SOI MOS is discussed.