The Design Of C8PSK-Based HART Modulator

HART is fieldbus protocol which has characteristics of transmitting digital signal on exiting analog transmission line.C8PSK refers to 8-way phase shift keying modulation technique. C8PSK-based modulator is communication module used in fieldbus controlling. It transforms statue and controlling data from kinds of equipments and meters to data form adapt to twisted-pair. It delivers controlling data from host computer to equipments, and delivers statue data from equipments to host for analyzing.In nowadays the modulator used in HART fieldbus is FSK-based, which use 1200Hz represent 1 and 2200Hz represent 0, and data rate is 1200bps. While C8PSK modulator can reach 9600bps data rate. Because there is no C8PSK modulator be developed out, this design make big sense. HART Physical Layer Specification speficy the signal transmission mode,this thesis focused on the design of C8PSK according to the specification.This thesis presents the system architecture first, and MATLAB was used to implement arithmetic and performance analysis. The thesis designs the C8PSK modulator according to standard digital IC process. First make module division, and then design the RTL code. This thesis improved the implementation method of the SRRC based on C8PSK data characteristics; obtain good balance between the implementation difficulty and system performance. It decreases implementation difficulty and reduces power consumption. Use UMC 0.18um standard cell library to synthesize the gate netlist and doing timing analysis. At last, use place and routing tool to generate layout.The function of the design was verified correctly with 100% code coverage and its timing satisfies the requirements after synthesis, setup and hold timing slack is 4.27ns and 0.33ns,and area is 11453um~2.Verification indicates that the design achieve the C8PSK physical layer specification.The C8PSK modulator can either be used as the IP embed into fieldbus controlling chip, or implement use FPGA to direct apply to fieldbus.