Design And Implementation Of Video Compression Protocol Based On Cradle CT3400

As the original video data is so voluminous for real applications, video coding has been a focus of research and applications for saving transport bandwidth and storage space. Meanwhile, modern DSP technology is developed and multi-core DSP is in the extensive application. On DSP software video compression coding has become an inevitable trend. So it's very important for us to have an in-depth study on the key techniques used in video coding, its realization under different hardware environment and performance optimization according to different environmental characteristics.In this paper, the optimization and realization of H.263 video codec on embedded multi-core processor is researched. The embedded processor used is a multi-core DSP for multimedia applications produced by Cradle Corporation. H.263 protocol is an ITU-T recommendation that for high-quality image compression at low bit-rate. It's applicable to video telephony, data storage, video viewing, video surveillance and other video applications. And H.263 is mainly applied in narrow-bandwidth video communication applications. CT3400, produced by Cradle Corp., is a 3SOC (Software Scalable System on a Chip) digital signal processor. It can support flexible software system, and can achieve a whole MPEG system including encoding, decoding, image processing and network transmission function in one chip.This paper firstly briefly introduces H.263 protocol and CT3400 hardware structure and characteristics, as the study background. Then it summarizes the main points and skills of using CT3400. This part helps for the further understanding of multi-core DSP and understanding of the characteristics and functions of CT3400. The focus of the study in this paper is the design and realization of H.263 on CT3400. For the purpose of reasonable and efficient use of the heterogeneous processors in CT3400, H.263 is basely divided into three parallel parts: encoder, decoder and input/output. These parts are allocated fix processors, and between these parts, there are no synchronization requirement and only one-direction data transmission. Then the encoder and decoder parts are divided into several functions modules. Before designing and implementing each module, the interfaces and communication problems between modules have been rational and well designed. Finally, the performance indicators and actually performance of the realized system on CT3400 is reported.Also, this paper studies and researches some compression algorithm which contained in functional modules. Particularly, the motion estimation algorithm is researched. Because the computing quantum of motion estimation is 60% to 80% of that of the total encoder, this algorithm enormous impacts the system performance. Meanwhile, for different type of video and different hardware, there have different optimal algorithms. In the last chapter, three new algorithms are proposed which fit particular environments. All the three algorithms are simulated and compared with other well-known algorithms, and the results are reported and analyzed.