Research On Hardware Acceleration Of Automatic People Tracking System

With the improvement in processing capability of computers, people tracking research has become a hot spot in computer vision domain. People tracking can be applied to many military and public situations, such as visual surveillance, MPEG-4 video compression, virtual reality and human-machine perceptual interface. Many software-based systems have been implemented, but the processing speed can not satisfy real-time tracking.The progress in semiconductor technology gives birth to high-speed and high-volume FPGA chips. New tendency of computer architecture design has appeared and software/hardware co-design becomes an important method. On the basis of deep research on current people tracking algorithms, we select some key algorithms as our research objective of hardware acceleration, and build a prototype of automatic people tracking.The people tracking accelerator in this paper has features as follows: due to the short of floating-point modules, we design a computing schema of resource sharing. Its structure and the method of mapping loops onto it are also provided. A pipelined multiplication-accumulation unit was brought forth which can accelerate the execution of computation intensive algorithms. To store and process the moving people regions, we propose and implement a parameterized linked-list memory. The list capacity and data width can be configured on demand without changing its internal structure.This paper implements an accelerator prototype by using Altera Stratix II FPGA chip. The system works correctly while testing some video clips, and has high speedup and real-time response to changes.In order to efficiently accelerate applications with bulk floating-point operations under constrained resource, we adopt software pipelining technique in computer architecture to design and implement a FPGA pipeline scheduler. It can generate a high performance pipelined data path automatically for a loop. In addition, a sparse interconnect consisting of shift register queues was designed to organize final circuits. At last, we extend and optimize the scheduler, analyze the FPGA pipeline performance, and give the upper bound of speedup in theory.