Design And Relization Of Motion Vector Predictor In H.264 And AVS Multi-Mode Video Decoder

In modern society, video information has become an indispensable element of human life, and the tremendous consumption needs of video decoding chip have led to unprecedented thriving of semiconductor market. Driven by the needs of market, research of video coding standards and corresponding hardware realizing method has become an important subject of both industrial and academic community.This paper has studied the inter prediction method of prevailing video coding standards H.264 and AVS, which stand for the leading video coding technology of the world, and tried to propose a hardware realizing scheme for a motion vector predictor, which can meet the needs of concurrent situation of multiple video coding standards and be flexibly used in multi-mode video decoding SoC design.First, the paper analyzed the present situation and bright future of video decoding semiconductor industry and also pointed out some conspicurity contradictions faced by this industry today, including the coexistence of multiple video coding standards, the high tension of design period and shotage of development cost. Then it brought out the meaning of our study.After that, this paper summarized the common inter prediction coding and decoding method. A detailed explanation of motion vector prediction process of H.264 and AVS was made and based on this explanation we analyzed the possibility of hardware sharing during motion vector prediction between these two standards, and also proposed an effective memory control method for the multi-mode motion vector predictor according to the circumscribing of these two standards; meanwhile,the paper proposed a complete scheme of hardware design for multi-mode motion vector predictor; introduced the detail operating mechanisim, interface and timing of the design;and described the design scheme module by module. Besides, the important and creative parts of the design, including the state machine of control module, the pipeline architecture of spatial prediction module, array divider with pipeline in scale module, and the scheme of memory controller, were declared in the paper with emphases.Finally , after introducing the design flow , environment of exploitation, and the simulation and verification method been used,the paper showed the detail results and reports of each stage of the design, including RTL simulation, synthesis, formal verification and Gate-level simulation. According to the compare and analysis of the experimental results, the paper drew a conclusion and forecast the future.