PEEC Modeling And Model Order Reduction Of Silicon-Based Integrated Passive Components

Integrated RF passive components, either in silicon based System on Chip (SoC) or System in Package (SiP), are the key building elements that construct a single-chip monolithic functional system. In the past few years, new configurations and modeling techniques for the passives in RF integrated architecture have drawing a great deal of attention. Needless to say, the characteristics of integrated RF passive components, e.g. the Q value of an inductor, will decisively determine the overall performance of the system. With the increase of the operating frequency, the inevitable parasitic effects together with the significant loss properties of both the substrate and the conductors become the major challenges to the designers. Even though the modern full-wave electromagnetic simulation software packages are more powerful than ever before, they still could not provide good intuitive insights of those parasitic effects and a good physically expressive circuit presentation, not mentioning the long computation time for large-scale systems.The Mixed-Potential Integration Equation (MPIE) based Partial Element Equivalent Circuit (PEEC) technique, which converts a circuit layout into a lumped RLC element coupled network, has been widely used in the modeling of integrated passives. However, the number of nodes and components in the generated circuit are usually excessively large, which makes the traditional SPICE-like circuit solvers extremely slow to run and is prohibitively difficulty to reveal the physical insights. Therefore, researchers have been searching for more effective measures that can reduce the circuit model order (Mode Order Reduction or MOR) to accelerate the circuit analysis, on one hand, from the system input-to-output response point of view. On the other hand, people have been looking for more appropriate circuit presentation from both physics intuition and the system responses. The main contributions of this work is focus on (1) discrete real images method based on Levenberg-Marquardt algorithm (LMA) is presented in the evaluation of quasi-static multilayered Green's function; (2) the PEEC modeling including various loss effects is utilized to analyze the frequency-dependent characteristics of several silicon based on-chip passive devices; (3) the derived physically expressive circuit (DPEC) model is employed to conduct model order reduction of the large circuit network. The DPEC based on a uniform treatment of complex capacitances and inductances simplifies the circuit model, but still preserves the main attributes of the original network. The case studies of several practical examples: coplanar waveguide, singlelayered and multilayered spiral inductors, on a silicon substrate are given to show the validation and effectiveness of the extended DPEC model. It can be seen, through the examples, that the frequency responses including: S parameter and Q values vs. frequency is very well preserved in the DPEC model, showing that the extended DPEC model for lossy circuits can effectively retain the essences of a lossy integrated passive circuit.