Design And Implementation Of Transmitting Card For Colorful And Dynamic LED Large Screen Display Based On DVI Protocol

With the advent of the information age, multimedia technology is developing rapidly. In many occasions, such as the universal application of network technology, the command control centers, the video meetings, we have more and more requirements to large screen, multicolor, high brightness, and high resolution display. But traditional CRT monitors are difficult to meet such demands. In recent years, the fast developing large-screen display technology is really an effective means to manage large colorful pictures, and it has extensive scope of applications. Consequently its market becomes more and more active because of the increasing demands.The technology of LED display integrates the optoelectronics, computer and computerized control technologies, and it is made up of four components which are display screen, a transmitting card, several receiving cards and the computer for control display. When LED large-screen needs colorful and dynamic display at real time, the transmitting cards must process much more data with higher efficiency. Available products usually achieve improved performance by adopting devices with relatively high price, which inevitably increase system cost and thus restricts the application of LED large screen. Therefore, it is necessary to find a way to reduce costs and improve efficiency of the devices.In this dissertation, DVI protocol and EDA design are introduced first with analysis on the character of the DVI protocol and the flow of EDA design. Then a transmitting card design scheme of LED large screen is proposed after deeply research on data load and speed of the transmitting card. Because of LED large-screen display colorful content dynamically at a real time, the transmitting card must work with heavy data load with high baud rate. We select FPGA which accounts for achieving the top speed for the communication between the transmitting card and receiving cards, the transmitting card and the computer. Through the time analysis of Ethernet,DVI interface,serial interface and SDRAM, function blocks are classified and finally coded with hardware description language VHDL. The code is optimized for increasing work frequency so that the cost-oriented FPGA can run at the 133 MHz with much less in-chip resources. Thus high quality data transmission can be guaranteed with reduced system cost. In this dissertation, design and optimization of the FPGA modules to increase speed and decrease resources are discussed, and finally it is implemented in a physical FPGA. Laboratory transmission and display test shows the feasibility and validity of this design.