Event-based Structural Operational Semantics Of Verilog

Along with the high speed development in the areas of digital communication and automation control and vehement competition all over the world, stricter requirements are proposed to digital systems. At present, digital circuits design ability is far behind the improvement step of manufacture technology, In digital logic design field, hardware description language (HDL) is used on hardware design to descript different level abstract design. In order to insure the correctness of development, an exact understanding of HDL is necessary.Among all of HDLs, Verilog is one of popular hardware depiction language in industry field. It can design and descript hardware based on behavior level and structure level, but the studies of its formalization are not sufficient, and it's IEEE criterion is also used un-formalized description. This may bring problems such as different running results from different editions and inaccurate understandings between designers. So a formal semantic which is defined for Verilog is needed to verify the equivalence of description and running results. Thus, we could improve correctness and reliability of developing system.Formal semantics is one of the Software Engineering basic theories. The formal syntax and formal semantics have become the essential composition of programming language. Operational semantics is a classification of formal semantics, it define semantic of the language through the realization. This paper introduces an important embranchment of concurrence model, which is also an usually expression tool in formalization method—Event Structures, uses it' t labelled events and Process algebra as basic mathematics frames, finally we give an enevt-based structural operation semantic of a subset of Verilog.