IP Core Design Of RPE-LTP Speech Codec Based On FPGA

RPE-LTP(Regular Pulse Excited — Long Term Prediction) speech codec algorithm is one of the standards for GSM(Global System for Mobile Communication). It adopts 20ms frame, each frame contains 160 speech samples. It's code rate is 13kbps and the quality of reconstructed speech can reach above MOS 3.6.DSP (Digital Signal Processor) is the favorite for most people to implement the RPE-LTP speech codec algorithm. This is for the state of the hardware technology's development in the GSM mobile communication setting-up period. Undoubtedly it was the best scheme to choose DSP at that time. With the development of integrated electronic circuit technology, there are more and more available implementation schemes for RPE-LTP speech codec.This subject is a part of the project "GSM/CDMA bimodulus cell-phone base-band physical layer's key technology research and the IP Core implementation". In this subject we put forward an implementation scheme of RPE-LTP speech codec algorithm by using FPGA and has finished the work of designing, programming, emulating the VHDL program, etc. And put forward several kinds of design methods on different needs through analyzing the characteristic and key technology of the algorithm in detail.After testing the IP core which we have designed to implement the RPE-LTP speech codec algorithm, the result is satisfying. The codec's whole delay is 5844 clock periods, and the clock frequency can up to 13MHz. It turned out that our implementation method can shorten codec delay greatly.