Design And Implementation Of WiMAX OFDM Physical Layer Using FPGA

With the increase of world economy and development of information technology, more and more users have the requirement of broadband access to data, audio and video. Traditional access techniques have become the bottleneck in the development of the next generation broadband communication networks, therefore broadband access is considered to be an inevitable trend. Among the numerous burgeoning access technologies, broadband wireless access has attracted the most attention from the communication industry during recent years, due to its particular advantages in system performance. As a emerging broadband wireless access scheme for WMAN (Wireless Metropolitan Area Networks), It is able to provide "last mile" broadband connectivity in a larger range than Wi-Fi, and it has a better mobility in the application of high-speed data.In the thesis, there is a brief introduction to the fundamental and characteristic of OFDM, application and develpment vision of WiMAX technology, current status and problem confronted of WiMAX is analyed .Design and implement of WiMAX OFDM physical layer transmitter using FPGA based on IEEE802.16d is presented. Each module of transmitter uses asynchronous processing architecture, with a high-frequency clock it predigest the design architecture and minish the hardware resources.Design and implement of WiMAX OFDM physical layer receiver using FPGA based on IEEE802.16d is presented. New optimize design architectures are presented for frame detect, estimation and revise of time domain fraction frequency offset, estimation and revise of frequency domain integer frequency offset, channel estimation, minimized the hardware resources with the assurance of system performance.A 64/256/1024/2048-point scaleable FFT processor is presented. It is based on the Radix-22 SDF (Single-path Delay Feedback) butterfly architecture, and is very suitable for usage in broadband adaptive OFDM communication system, where variable number of sub-carriers, high throughput, low latency and configuration flexibility is required. Considering the OFDM waveform characteristics, the output SNR and logic cell consumption with respect to different internal word-lengths and rotation factor quantization precisions are simulated and analyzed. Then implementation parameters are appropriately selected, which leads to a higher output performance while a less hardware consumption.A new architecture for variable shorten-erasure Reed-Solomon decoder/encoder of IEEE802.16d is presented. We adopted symmetric generator polynomial to reduce the number of Galois field multiplications in encoder, while in decoder, we solve the key function by change the initial condition of the MEA(Modified Euclid Algorithm) and present a newdecoder architecture based on conventional architecture, which isn't suitable for decoding shorten-erasure Reed-Solomon codes. We analyzed the maximum decoding throughput of six variable shorten-erasure Reed-Solomon codes stated in IEEE802.16d at specific clock frequence, which is benefit for implementation of a IEEE802.16d system.