Processing Of Fluxgate Output Signal Based On FPGA

Since the acceleration of digital advancement, our society is going into digital times. Since the development of DSP technoplogy and FPGA, the hardware system designed by FPGA device is easily made into chip production, so online rework is easily. The circuit designer can via hardware programming to achieve specifically digital procession arithmetic. This thesis aiming to characteristic of fluxgate signal procession and collection investigates, discusses the fluxgate signal processing sysytem based on FPGA. Because the traditional fluxgate output signal is commonly processed by analogy circuit and the characteristics of temperature is a little bad, especially the cost of improving the characteristics is higher, but the temperature characteristics of digital processing system is better and application of the digital processing system to prosess the fluxgate output signal is not much, the main purpose of this thesis is to design digital processing system to improve the characteristics of the temperature of analogy circuit.This thesis discussing the designing process and working theory, simulates and validates design scheme fit to the system. Based on commonly frame of digital processing system, our system can separate into two departments-outside slice A/D circuit and inside system design. In the inside system design we use FPGA as the carrier of system and emphasis discuss modularization design of inside system. In the design process we base on the function to divide the system into different blocks, and we use the method of separately design different blocks of system.In the design of digital processing of fluxgate out put signal system, this thesis separately designs the block of A/D controlling, commutating, FIFO, digital procession and vision, in the end discusses the integer system design and magnetic field values. In the whole design we use simulation tool ISE to carry out the" from top to bottom" design scheme, we carry through system modeling at first and then use VHDL language to describe different blocks. When all the source codes are finished, we can compile test bench file to simulate the different block and integer system, at the same time analyzes the simulation result.