The Front-end Design Of The Contactless Tag IC

Based on the deep study of the technologies about the tag, this thesis presents a design scheme of the tag IC operating at 13.56MHZ, according to ISO15693. After finishing the functional specification of the tag, we partitioned the chip IC into sub-modules, defined the interfaces, and then designed the sub-modules individually; finally, we simulated all blocks together and finished the front end design of the tag IC. The tag chip can be partitioned into three functional blocks which are RF front end module, digital control module and Memory. The direct schematic design of some sub circuits had also been conducted in reference to other function-like circuits, using the "Bottom-to-up" methodology. Digital block was partitioned into hierarchy modules firstly, the RTL coding of sub-modules have been simulated in ModelSim. The thesis presented the scheme of RF front end, interface, digital module, and analyzed the pivotal module and circuit in detail. The last chapter discussed the reliability method that RFID system takes. For the tag IC, it is hard to gain enough power from the carrier wave, so the Tag IC must have the feature of low power. To reduce the cost, the tag IC can not consume more area. We always followed the principle of low power and low area, and we take the method of multi-power and multi-clock to decrease power. On the premise of good function, concise circuits are adopted to reduce area.