The Implementation Of Fme In 1080P Video Encoder

H.264 is the most advanced video coding standard, it has excellent coding performance and good network adaptability, however, its computational complexity is much more than all previous video coding standards, especially in the inter-frame encoding process. The motion estimation process takes most of the coding time due to the use of techniques such as Variable Block Sizes Motion Estimation, Multi-frame Motion Compensation and Rate Distortion Optimization (RDO). Integer-pixel Motion Estimation (IME) module completes the coarse match of the block to the reference frame, and Fractional-pixel Motion Estimation module gets the refinement basing on the IME result, controlled by RDO with 1/2-pixel then 1/4-pixel accuracy, and ultimately the macro-block coding mode and motion vectors are obtained. For 1080P high-definition (HD) video, there are 8160 macro-blocks in a frame, thus the FME module has a great effect on the performance of the real-time encoder.A pipeline-architecture was proposed with scaled searching algorithm based on the analysis on the previous work and the consideration of the system requirement between chip area and performance. The design was divided into 1/2ME and 1/4ME 2 stages, and the micro-architectures of each stage were implemented.A pipelined architecture with two 1-dimension interpolation for 1/2ME was proposed to meet the needs of HD video encoding, resulting in lower complexity and higher throughout. The interpolation and SAD calculation element were integrated into one unit, resulting in better performance in 1/4ME module. The design accomplished FME for one MB within 150 clock cycles, capable for 1080P@30fps HD applications. The functions of the design were verified by the reference C model. Synthesized with Chartered 0.13μm process, the design consumed 140.8K logic gates, with peak frequency of about 150MHz, and consumed about 27mW at the power supply of 1.20V.