Fpga-Based Acceleration Of Plasma Finite-Difference Time-Domain Method

In this paper, we discussed how to use Field Programmable Gate Array (FPGA) to accelerate the plasma Finite-Difference Time-Domain (FDTD) algorithm. FPGA has both the flexibility of software design and the speed advantage of application specific integrated circuit,and FPGA is also very suitable for parallel computing, pipeline processing and fixed-point arithmetic. So it is very convenient to accelerate the plasma FDTD algorithm, which structure support parallel optimization very well.First, we introduced FPGA application of 1-D plasma FDTD algorithm. In this design, we used the fixed-point presentation for the value, we optimized the algorithm and memory interface, and numbers of updater modules were used and they were linked with a few memory blocks through multiplex. We implemented a 1-D plasma FDTD algorithm based on FPGA. The results show that the new algorithm has a higher speedup with an acceptable accuracy.Then we introduced how to accelerate 2-D plasma FDTD algorithm. We still used the fixed-point numerical presentation, but we used general update module and connected it with a whole memory block, so we could update all the value with the same update module, and then got a more clear structure and less resource cost. We verified this design with a 2-D plasma FDTD numerical example. The result indicates that we can also speed up the design with high accuracy, and has a good balance between resources and speed.Finally, we analyzed how to implement 3-D plasma FDTD algorithm based on FPGA. First we predicted the feasibility according to our design experiences in the 1-D and 2-D design, then the problems we may face in the process of design, and we also provided solutions for these problems. These discussions should be useful for further research.