The Research And Design Of The Visual Inspection Model Based On FPGA

Visual inspection technology is applied in the areas of modern production, medical equipment more and more widely. Edge detection and restoration of motion degraded images is the important content in the research of visual inspection. The image edges contain most information of the image,edge detection is the key step of image processing and analysis, and has significant influence on the high-level description, matching and recognition of characteristics. On the fast detection of the product quality based on machine vision, image motion blur is an important factor that affecs detection accuracy. The effective method of solving image motion blur is the corresponding recovery processing according to the reasons of motion blur.The wide application of the field programmable gates array (FPGA) in industry has advanced the position of the digital image processing realization based on FPGA. Modeling design is a kind of the top-down rapid prototype validation method facing the FPGA,it not only reduced the FPGA design threshold, and shorten the development cycle, improve the design efficiency. This makes the FPGA modeling design became the trend of FPGA system design development. Aiming at the common image processing algorithm of visual inspection based on FPGA modeling, research and design were carried out in the following several aspects.This paper first introduce the software tool of modeling design method:System Generator and AccelDSP.Secondly introduced the design model in detail on edge detection and image restoration algorithm with the System Generator in Simulink environment, and simulating in hardware and generates HDL code. Finally carry out AccelDsp modeling design on edge detection and kalman filtering, not only the seven edge detection operator transverse comparison were made in the same kind of FPGA to hardware implementation, but also the longitudinal comparison of the same kind of the kalman filter algorithm were made in five different types of hardware implementation on the FPGA. Produce, verify, and analyzes the fixed point model and floating-point model of RTL (register transmission level) model and comprehensive analysis, comparing different list comparison experiment process, results and resources consumption.This design has the following innovation points:(1) differing from traditional algorithm development method, image processing algorithm of visual detection is developed by AccelDsp and system generator combined with matlab/simulink and ISE in this paper. Experiments show that, can yet be regarded as a kind of fast and efficient design method.(2) developing algorithm model, in the process of hardware realization, not only transverse comparison of many kinds of algorithm were made in hardware, but also longitudinal comparison of the same kind of algorithm were made in various types of FPGA. It provides an effective thinking for analysis and modification of the choice of algorithms and hardwares...