Research And Implementation Of Authentication Algorithm For High-Speed Network

With the development of communication technology and the appli-cation diversification of the networks communication upper layers, more and more bandwith resource is required by the endpoint users. In order to meet the requirement of the high speed networks such as EPON, GPON, 10GEPON etc, it is believed that the security issues on the high speed networks become imperative to be resolved. The security technologies used for traditional low speed networks can not meet the current high speed networks needs. Hence, how to effectively protect high speed networks communication security becomes the research hotspot currently. In order to resolve the authentication security issues on high speed net-works, it is deeply researched on the authentication technology called GMAC used for high speed networks in this thesis. Then, it proposes the architecture design of the GMAC hardware implementation, which is called high performance GMAC implementation wirh low space com-plexity and low time complexity. Subsequently, it gives out the analysis on consumption of hardware resource and the delay of the critical path. At last, it also gives out the simulation and synthesize of the GMAC im-plementation design on FPGAnic. In order to get more information about the implementation effect of GMAC, it designs one kind of architecture GMAC implementation suit to gigabit Ethernet environment. It is com-bined debugging using the GMAC IP Core and GE MAC IP Core on FPGAnic platform. Based on these work, it proposes the network level test to validate the algorithm implementation. The test report indicates that the GMAC architecture design meets the requirement of the high speed networks authentication security.This thesis's main work and the relative are listed as following:1. Based on the current mainstream technology of message integrity checking, this thesis discusses and analyzes the typical block data mode of authencication. It stresses on analysis of the GMAC authentication technology.2. Through the analysis of GMAC operation mode, this thesis gives out the implementation of GMAC architecture. Then, the analysis and simulation results are given. On the basis of the above, this thesis pro-poses the optimal architecture of GMAC in order to get high performance. These optimized architectures include the parallel structure design for higher throughput and two kinds of pipelined structure design for higher performance.3. Based the work on the GMAC architecture design mentioned in the 2nd item, this thesis makes the architecture design suit to the FPGAn-ic platform, and debugging with GE interface.4. Based on the implementation of the GMAC mentioned in the 3rd item, this thesis designs the methods to validate the GMAC on algorithm and networks level.The full text is organized as follows:The 1st chapter discusses the research background, points out the research status of the domestic and foreign related authentication tech-nology and the trend of the authentication security technology.The 2nd chapter introduces the algorithm principle of GMAC and its key function Ghash, which is the key component of the GMAC function implementation.The 3rd chapter researches the architecture design and optimal of GMAC. This chapter firstly gives out the basic architecture of GMAC following the GMAC algorithm. Then based on the basic architecture of the GMAC, it proposes the optimal structures, which include the parallel structure of GMAC and two kinds of pipelined structure of GMAC.The 4th chapter gives out the analysis on the GMAC architecture mentioned in chapter 3rd. This part is mainly about the analysis on throughput and the complexity. The higher throughput of GMAC can be archieved by the parallel structure of GMAC, and higher performance (low space complexity and low time complexity) of GMAC can be arc-hieved by the pipelined structure of GMAC.The 5th chapter researches the GMAC high speed implementation on FPGAnic platform with the combined debugging between GMAC IP Core and GE MAC IP Core. Then, this part designs the test to validate the GMAC implementation on FPGAnic platform on algorithm and networks level.The 6th chapter is the summary on the research results of this paper.