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Research On Partitioning Algorithm Of HW/SW Co-design

Posted on:2006-04-21Degree:MasterType:Thesis
Country:ChinaCandidate:X Q WangFull Text:PDF
GTID:2168360155968942Subject:Computer software and theory
Abstract/Summary:PDF Full Text Request
Hardware/software codesign is an important research field of SoC. It is widely existed in embedded system. ISA and IP based system design. While HW/SW partitioning is a critical step in the codesign, the partitioning result has direct effect on the performance of the system. Targetting the shortcomings existed in traditional algorithms, this paper mainly do two contributions, one is introduce a guiding function for greedy partitioning algorithm and another is improved traditional simulated annealing partitioning algorithm.First, this paper describes conception and issues existed in HW/SW partitioning, introduces in detail about computing model and hardware architecture that are two important factors effectting HW/SW partitioning. Next, studies the partitioning algorithms targetting coprocessors architecture consisted of microprocessor and FPGA, in which choose PmG as the computing model.Traditional partitioning algorithms have the shortcoming of neglecting effective use of hardware resource. The main work of this paper is that it has improved two algorithms in this respect. Targetting parameterized FPGA coprocessors architecture that includes three types, static reconfigurable, whole dynamically reconfigurable and partly dynamically reconfigurable, guiding function based greedy partitioning algorithm can automatically explore the design space. The guiding function is decided by the criticality, speedup, probability and area of a task, which not only improves the hardware resource use efficience but also takes care of the task on the critical path at the same time, so the algorithm can get an appropriate optimum solution. The improved simulated annealing partitioning algorithm use dynamic weight for the two metrics time and area in its cost function. For a move, considering both performance change and area change at the same time, which can make full use of hardware resource and speedup the partitioning speed. It is proved that the improved simulated annealing partitioning algorithm is prior to traditional one in partitioning time and result. In the end. this paper analyses the experiment results.
Keywords/Search Tags:HW/SW partitiong, reconfigurability, guiding function, greedy algorithm, simulate annealing
PDF Full Text Request
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