The Research Of Image Compression Coding Based On Wavelet Transform

Image information is an important headspring for people to know the world and ourselves. But the data quantity of image is huge, which not only requires high storing and operating capacity for computers, but also restricts the channel transfer rate of image communication. Therefore, in order to store, process and transfer the data, compress processing must be done for image information. This paper discusses it in such condition. Firstly, this paper discusses wavelet selection for image. The emphases of this part are the characteristics of the image coefficient distribute, gradation histogram, image itself, after wavelet transform. The reasonable bases for image compression are obtained after wavelet transform. Embedded image coding using zerotrees of wavelet coefficients (EZW) algorithm is researched and simulated. On the basis of it, the disadvantages of this algorithm is analyzed and an improved algorithm——EZW which reserves low frequency components. The simulation of the algorithm is realized, and the results show that the algorithm can improve the peak signal noise ratio (PSNR) and reduce the mean square error (MSE) compared with EZW. Secondly, this paper researches the theoretical basis of fractal coding, focusing on iterated function system (IFS), collage theorem, attractor theorem, and so on. Sierpinski carpet is simulated using Matlab. Based on IFS, image compression coding method is researched and realized. The advantage of taking too much time in fractal coding is obtained. So that the fractal coding in wavelet domain——lossless coding for low frequency components and subtree fractal coding for high frequency components is proposed. The simulation of the algorithm is realized, and the simulation results show that the algorithm not only shortens the coding time, but also improves the compression ratio. Finally, TMS320C6201 being the kernel, an image compression coding algorithm is given to achieve the scheme for hardware realization. In addition, the design scheme for connecting the DSP chip with peripheral equipment is discussed, and, in the meanwhile, relevant apparatus parts and the compression process are given.