Research On Error Concealment In Video Communication And Video Optimization Based On DSP

With the worldwide popularization of computer and network technology recently, the human being has entered the digital information era. At the same time, the need of information and communication has no restrict of space and time, and the video communication has been one of the hotspot in the information and communication area. Furthermore, the coding, storage, processing of video is the core area of the video communication.Under the support from The National High Technology R&D Program (No. 2002AA119010) - "Demonstration System of Digital Audio/Video Codec, Transmission, Testing and Application" and "remote video monitor and control system based on multimedia communication", the work introduced in this dissertation has researched postprocessing error concealment of video decoder and the implementation of real-time MPEG-4 video encoder based on DSP. The dissertation is organized as follows.Firstly, an overview of the characteristics and standards of video communication and compression is given, which illuminates the research content of this dissertation. Then, some key points of the latest video compression standard - H.264 is presented. And the simulation platform of wireless communication and the experiment of the transmission of H.264 based on it is brought out. After that the error concealment technologies in the recent year are reviewed, and the algorithm adopted by H.264 is described in detail. Meanwhile, the advantage of multiframe error concealment and the disadvantage of it in the scene change are analysed.Then,a new multiframe error concealment algorithm based on scene change detection is proposed. The experiment result shows that, this algorithm has a better performance in the situation of abrupt and gradual scene change than the original multiframe error concealment. Then the MPEG-4 codec based on Philips Trimedia DSPs is discussed. And the focus is the implementation and optimization of the codec. A lot of work ranged from algorithm optimization,code optimization to instruction optimization have been done. While a problem with the VLIW DSPs is that the speed of CPU processing is not compatible with that of the off-chip accesses to main memory, which is responsible for CPU process delay. Thus it becomes a bottleneck of DSP performance. A new data-layout algorithm for video data processing based on DSP CPU according to the Cache Architecture is provided. And it is applied to the optimization work successfully. The encoding results demonstrate the effectiveness of this algorithm in eliminating Cache misses and Cache bank conflicts. Furthermore, it reduces the cost of off-chip accesses. And the encoding performance has increased about 2f/s (CIF) with this algorithm.Lastly this dissertation is concluded and future research directions are discussed.