Design Of ECG Front - End Detection Circuit Based On

Nowadays as people’s living standards improve, they pay more and more intentions to their physical health, and the most important of all, is the heart. Semiconductor industry has developed greatly in the past few years, they can be easily found around us. In the present,semiconductor technology is one of indispensable technique in the scientific progress.In this paper, By analysis of the features and designing the front-end testing circuits for ECG signals, we design an ECG signal front-end testing circuits. Circuit has low noise, low power consumption, higher common mode rejection ratio, etc. ECG signal detection circuit consists of two levels of op-amp structure, feedback circuit, bias circuit and compensating circuit, and using Cadence software carries on the simulation analysis, finally draw the circuit layout and DRC, LVS verification.The chip is made by UMC 0.18μm CMOS process, the area of the core circuits is 0.0099mm2. Testing results show that under single supply of 1.8V, equivalent input noise of the front-end testing circuits is 5.063μV. In the 143.3Hz, the gain is 47.79 dB. Power consumption is less than 46.18μW, and common mode rejection ratio 90.89 dB, power supply rejection ratio 75.17 dB.It suggests that the chip would basically meet the requirements of ECG signal acquisition.