Design Of Dual Synchronous Step Down DC/DC Regulator IC

On the basis of the project of the Institutes of Circuits CAD, "Design and key theoretical research of multiple outputs DC/DC regulator", a dual outputs high efficiency current mode synchronous step down DC/DC is designed and a deep study of Buck DC/DC theory is carried out. The whole simulation of the chip has been completed with HSPICE, and the simulation results match the design specifications.After a systemic study on the current-mode switching regulator, the high efficiency current mode synchronous Buck DC/DC regulator XD4982 is designed featuring dual outputs. By adopting the technologies of synchronous rectification, two optional operation modes at light load and drop-out operation, the efficiency of the chip is up to 96%. A special slope compensation circuit, which increases the slope proportional to the duty, is designed to prevent the sub-harmonic oscillation at large duties. Due to the clamp circuit which adjusts its thresholds with respect to the magnitude of the slope compensation, two regulators remain a substantially constant maximum current limit in all duty cycles. A reference voltage far away from the bandgap is determined by a current which is determined by a current refernce circuit controlled by the bandgap voltage, and the reference voltage confirms the stability of the chip. Two kinds of small signal models of Buck DC/DC are discussed to analysis the dynamic performance of DC/DC. The loop compensation is precisely designed considering of the stability of the control loop. Two regulators share the same clock and run in-phase, and the chip can be synchronized to an external clock signal, and provides good noise performance.