Study And Design Of Low Voltage LDO

This thesis introduces the basic principle of LDO (low dropout linear voltage regulator), and discuss how to design and optimize LDO. According to this discussion, a low voltage, high PSR(power supply rejection) LDO is designed .LDO is composed of BGR (bandgap reference), Error Amplifier, Pass Element, and Feedback network. The PSR of LDO is decided by the voltage gain and bandwidth of error amplifier. In order to boosting the gain of error amplifier, a one stage, cross coupling charge pump, the structure of which is suited to low voltage application, is used to rising the power supply of error amplifier. LDO compensation scheme is the ESR(equivalent series resistor) compensation. Parameters of LDO's modules are optimized, based on analysis of LDO. Simulations based on Hspice and layout of LDO are completed.The designed LDO is simulated on 0.18μm CMOS process. The results show that when the input voltage is between 0.65V-1V, the output voltage is 0.5V, and the maximum output current is 200mA. PSR is -78dB at 1kHz, line regulation is 0.017%/mV, when Iout is 100mA, and road regulation is 0.020%/mA, when Vin is 0.9V. Low operational voltage and high PSR are realized while performances are optimized integratedly.