| Supported by the research project of Institute of Electronic CAD-"Theoretical research and design of key techniques for deep-submicron power management IC", this paper analyzes the design and related theory of Buck DC-DC regulator in detail. And a high efficiency current mode Buck DC-DC regulator XD1106 for portable applications is designed. The whole chip is designed in 0.5μm standard CMOS process, simulated with Cadence and Hspice simulation tool, the simulation results show that all specifications are met.By adopting the technologies of synchronous rectification and LDO mode at light loads, the efficiency of the chip is enhanced at whole load range.To further maximize battery life, when input supply voltage decreases towards output voltage, the duty cycle increases to 100%, which is the dropout condition, and the PMOS switch is turned on continuously. As a result of the adoption of peak current mode PWM control, the transient response speed of the supply voltage and the load's variety becomes much faster. In order to avoid the current loop instability, a new piecewise linear slope compensation circuit is designed. A clamp circuit whose threshold can be adjusted with respect to the magnitude of the slope compensation signal is also designed to cancel the slope compensation effect on current limit. Based on analysis of voltage loop frequency compensation, stability is realized through internal compensation. Over voltage protection circuit, over temperature protection circuit and other protection circuits are designed, which make the system more reliable and stable.
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