Parallel Controller Design Based On FPGA

The design for hardware is convenient just as designing the software, for appearance of FPGA and VHDL. The architecture and working of FPGA can be reprogrammable. The width of data is much longer than the word width of current computer in the condition of security for network information. It is lower speed and inefficiency for encryption and decryption just by software alone, and difficult to suit high-speed network. So it is propitious to ensure the security implementing the encryption and decryption algorithms by FPGA.A Micro-Controller described by VHDL with variable processing word's length process real-time data rapidly, which based on reconfiguration of FPGA. The customers can design outward multi-processor according to their requirement, and micro-controller will allocate every processor for parallel running. It can be used for encryption and decryption of information at network communication security. Reconfiguration of FPGA can reduce failure risk when change of requirement leads a new design. A new logic design according to a new requirement and reconfiguring FPGA can fulfill the new task. Utilizing parallel processing ability of FPGA, a real micro-parallel processing controller has been designed. The controller has realized parallel running and will improve the processing speed.This paper presented the design architecture of separate controller and processor. It adopts Harvard architecture. After separating controller and processor, each module of controller use RS (Require, reSponse) protocol to communicate with each other, which has solved the problem of that each module limits whole system's speed. The processor can be designed as a outside module for different application requirement. A register is used for serial input and parallel output. So the processor's word length is not limited, and it is convenient to design special outside processor. Each processor is independent. They can be running at the same time. This has improved the system's capability and efficiency. After this controller has fixed, designing new outside processors is spent less time. It is a convenient examination environment used for teaching and study.