Design And Implementation Of DDRII SDRAM Controller

Nowadays, as the technology of communication and multimedia developing fast, it is more and more important for memory technology. DDRII SDRAM as the second generation of DDR memory technology already be used widely, satisfies the requirement of the system greatly. The research and implement of DDRII SDRAM controller is making sense and valuable.DDRII SDRAM controller in paper acts as an intermediate stage between the system and external DDRII memory. Its primary responsibility is to access DDRII SDRAM memory according to system's requirement. The amount of coding is quite big, especially in the data path which exists the problem of arbitrating multi-path data and crossing multiple clock domains, the design architecture is approved to having big influence on the performance. From the performance and frequency standpoint, making DDRII memory internal bank read and write information visible, setting bank address as low address and choosing shifter to control all the timing sequence, this design realizes command dispatch mechanism timing optimization, improves performance and bandwidth usage. This design analyzes the timing window in detail when capturing data and makes the data path delay configurable, to improve the stability integrated in system, and adds a powerdown control module in the design, which will set DDRII memory into power_down mode to decrease power assumption when the external DDRII memory not be accessed for long time .This thesis first introduces DDRIISDRAM working timing characteristics and its controller functional and timing requirement, then builds DDRIISDRAM controller architecture, describes implementation and verification in detail. Further, the thesis compares the controller with Altera company's DDRIISDRAM controller IP core in performance and bandwidth usage, which proves the performance for design to be a little better than Altera controller IP, achieve a quite high level.