Research And Implementation Of Real Time Preprocessing Method For Stellar Map

As the application fields of digital image processing extend continuously, real-time processing technology of the digital image processing has become a hotspot of research. Today's VLSI technology provides this processing technology with a physical base--FPGA, especially in the real-time pixel-level image processing. Using the star images shoot by CMOS vidicon, system can calculate the instantaneous direction of axis of the star sensor in inertia space through such steps as star detection, identification of star clouds and ascertainment of position, so it can decide the three abstract axes position of a carrier. Locating the star precisely is necessary for the sake of star identification. Star image noise must be filtered and Centroid Locating must be calculated at the same time. Then using flag registers to store data temporarily, single pixel noise can be filtered by connective region technique.Based on the analysis of star image shoot by CMOS star sensor, the appropriate threshold value and Centroid Locating with threshold are calculated. Two state machines are designed to implement image segmentation and Centroid Locating calculation separately, and the Centroid Locating data is stored temporarily in a group of DPRAMs. Centroid-Locating calculation is carried out with Altera's divider IP core and pipeline technique. The resolution of calculation is 0.1 pixel and throughout is 10 frames per second (512*512 pixels per frame).When it connects to ARM, driving circuits (sequential logical circuits) is necessary because CMOS star sensor doesn't belong to I2C bus circuits.The CMOS star sensor driving circuits are made up of 5 modules, and they are interface module, communication module, frame module, row module, column module separately. The driving circuits meet all the requirements of CMOS star sensor STAR250 data sheet and the special processing speed requirement of 10 frames per second. The whole processing system based on CMOS star sensor has been verified using Altera's PLD--EP1S10B672C6. The practical FPGA verification results denote that design's function is correct.