General Hardware Platform Design And Validation For Single Frequency Software Defined GPS Receiver

With the current development of software radio technology, software GPS receiver has been a hot proposed solution meeting flexible and various application requirements, and now is leading various receiver research and development of BeiDou and Galileo systems to multisystem navigation. Multisystem singal simultaneous acquisition, united calculating and processing are required to implement on a general hardware platform for difference bettwwen these satellite systems and compatibility in integrated navigation, But platform for these applications has not been come forth. This research is to develop such a hardware platform with current various data acquisition techniques, and then validate it as a try for future integrated navigation and compatible receiver development.The paper begins with reviewes and summaries about GPS system structure and principle, software radio and GPS receiver technology, signal acquisition, prcessing and transmission techniques. Based on the typical structure of software GPS receiver, function requirement for single frequency software GPS receiver is analyzed into three terms clearly, which involves GPS singal acquisition, base band algorithm supporting and data and function opening demand, and then the hardware platform solution is proposed with NJ1006AK and TMS320C6416. After that, the mainly used integrated circuits, circuit design, firmware and PCI driver are all introduced detailly. In the last part, the feasibility and rationality of entire hardware platform are proved by spectrum analysis of actual acquired GPS data and Fast Fourier Transforms delivery.Based on NJ1006AK and TMS320C6416, this general hardware platform captures GPS signal via NJ1006AK, then receive it by Mcbsp (Multi-Channel Bufferd Serial Port) interface, driving EDMA (Enhanced Direct Memory Access) by Mcbsp receiver event to work in Ping-Pang buffer mode in external extended SDRAM. The data synchronization of base band processing is obtained by EDMA millisecond interrupt, in which PCI interrupt from DSP to host PC is triggered for communication between TMS320C6416 and PCI driver. Furthermore, ST16C550 is extended as on momery interface to help data and function opening as a low data rate serial port.The proposed solution takes full advantage of DSP internal Mcbsp, EDMA, PCI and other hardware resources, and achieves concurrent CPU caculating with high speed real-time continuous signal acquisition. This solution implemented with just a few integrated circuits, and simple standard external interfaces is very suitable for a general hardware platform, which is foundations of future multi-system navigation and compatible receiver development.