Research On High-speed Silicon Photonic Modulators And Integrated Chips

Driven by applications such as optical communication and optical interconnection,integrated microwave photonics,etc.,photonic integrated circuits（PICs）based on the silicon on insulator（SOI）platform can overcome the electronic delay bottleneck of traditional copper interconnects,providing optical solutions with large bandwidth,high speed,low power consumption,and low latency.The silicon photonic platform is compatible with the complementary metal oxide semiconductor（CMOS）process,providing very important benefits in terms of volume manufacture and cost reduction.Additionally,it can utilize the advanced packaging process of CMOS to realize compact,low-power,and high-density optoelectronic integrated chips.As one of the core devices of PIC,silicon-based electro-optic modulators modulate an external electrical signal onto an optical signal for transmission and processing in the optical domain.The metrics of silicon-based modulators,i.e.,high modulation efficiency,low insertion loss,and large modulation bandwidth,are key to achieving photonic integrated circuits with high capacity,low power consumption,and a large dynamic range.Therefore,this paper addresses the trade-off between efficiency,loss,and speed of silicon-based travelling-wave Mach-Zehnder modulators and conducts a study on high efficiency,high linearity,and high-speed silicon-based modulators in terms of physical mechanisms,theoretical simulations,and process preparation.Due to the widespread use of silicon-based electro-optical modulators in microwave photonics as well as optical communication and optical interconnection,two types of silicon photonics integrated chips are proposed and demonstrated in this paper.The one is an optical single sideband modulation integrated chip with a high sideband suppression ratio,and the other is a 4-level pulse amplitude modulation（PAM4）optical transmitter integrated chip with high energy efficiency and a large capacity.The primary research content and novelty of this paper contain the following aspects:（1）The slow light Mach-Zehnder modulator based on the direct current（DC）Kerr effect is proposed to overcome the bottleneck of the conventional plasma-dispersion-effect-based travelling wave Mach-Zehnder modulator in terms of insertion loss,modulation efficiency,and modulation bandwidth.The high modulation efficiency,high linearity,and high speed of the device are demonstrated.The reverse-biased PIN junction is embedded into a one-dimensional waveguide grating in order to enhance the DC Kerr effect,and thus the modulation efficiency is improved from 2.25 V·cm to 0.58V·cm.The proposed device has better linearity than the conventional slow light modulator.The spurs-free dynamic range corresponding to the third-order intermodulation distortion is improved from 104 d B·Hz^2/3 to 115 d B·Hz^2/3.To address the microwave-lightwave speed mismatch of the slow light modulator,a speed-matching structure using a radio frequency（RF）slow wave electrode to drive the slow light waveguide phase shifter is proposed.The slow wave electrode increases the parallel capacitance,and thus the microwave refractive index is increased from 3.7 to7.1,overcoming the issue of bandwidth deterioration caused by speed mismatch.A bandwidth of 67 GHz and a bitrate of 100 Gbit/s non-return-to-zero（NRZ）signal are demonstrated using the device.（2）A silicon-based optical single sideband（OSSB）modulation chip that is integrated with a RF branch line coupler is demonstrated.The degradation of the OSSB signal caused by the limited extinction ratio of the dual-parallel Mach-Zehnder modulator and the power imbalance and phase non-orthogonality of the RF branch line coupler is addressed by an optical domain modulation technique that aims to achieve a high sideband suppression ratio of the full carrier and suppressed carrier OSSB signals.The silicon-based dual-parallel modulator has a modulation efficiency of 1.75 V·cm,a bandwidth of 48.7 GHz,and an extinction ratio larger than 30 d B.The optimal operating frequency of the branch line coupler is 21 GHz,at which the output RF signals are equal in amplitude and 90°out of phase.It is demonstrated through theoretical calculations and experiments that although the performance of the branch line coupler in terms of power balance and phase quadrature deteriorates over a wider frequency range,the integrated chip can still achieve a high sideband suppression ratio by adjusting the optical power splitting ratio and the associated bias phase of the dual-parallel modulator to compensate for the detuning of the RF signal in the optical domain.With this technique,the undesired sidebands are completely suppressed below the noise floor in the frequency range from 15 GHz to 30 GHz when the chip operates in the full carrier OSSB mode.In addition,a sideband suppression ratio>35 d B and a carrier suppression ratio of 42 d B are demonstrated at 21 GHz in the suppressed carrier OSSB mode.（3）An 8-channel silicon-based PAM4 optical transmitter chip based on local area network wavelength division multiplexing（LAN-WDM）is demonstrated.In this transmitter chip,8 traveling wave Mach-Zehnder modulators,8 monitoring photodetectors,a flat-passband 8×1 multiplexer,and 12 edge couplers are integrated,featuring high integration,high capacity,and high energy efficiency.The performances of the individual components are as follows:The insertion loss of the edge coupler is about 2 d B/facet;the half-wave voltage,bandwidth,and insertion loss of the traveling wave Mach-Zehnder modulator are 8.8 V,～60 GHz,and 3 d B,respectively;the responsivity of the photodetector is greater than 0.9 A/W;the channel spacing of the multiplexer based on cascaded Mach-Zehnder interferometers is 4.4 nm,the thermal tuning efficiency of heater is 18.4 m W/π.The overall insertion loss of the packaged chip is 14～16 d B.106 Gbit/s PAM4 with a transmitter dispersion eye closure quaternary（TDECQ）of 1.37 d B and an outer extinction ratio of 6.52 d B is demonstrated for a single lane.For both linear and nonlinear impairments during the modulation and transmission of high-speed signals,the digital signal processing algorithms of cascaded neural network and maximum likelihood sequence estimation are utilized to effectively reduce the bit error rate（BER）of signals in the system’s transmission.170 Gbit/s NRZ and 250 Gbit/s PAM4 are demonstrated with BERs below the 20%soft-decision forward error correction（SD-FEC）threshold（e.g.,2E-2）for a single lane.For all 8lanes of the transmitter,total bit rates of 2 Tbit/s PAM4 signal over 1 km single mode fiber（SMF）transmission and 1.6 Tbit/s PAM4 signal over 10 km SMF transmission are also demonstrated.Finally,the total power consumption of the transmitter chip is calculated to be 361 m W,and the corresponding energy efficiency of 1.6 Tbit/s PAM4is 226 f J/bit.The performances listed above have attained a top ranking both domestically and internationally.