Research On The Key Technologies Of Compiling Of Heterogeneous Multi-Core System-on-Chip

Since the advent of the microprocessor,the number of transistors has continued to increase,and on this basis,its architecture has continued to innovate,so the performance of the microprocessor has continued to improve.Multi-core architecture is the latest architecture of microprocessors,and its hardware architecture is basically mature.Application compiling software is an important method to exert multi-core parallelism and computing power.Heterogeneous multi-core system-on-a-chip architecture is a processing architecture with remarkable features,outstanding computing power and broad application prospects.Since it was proposed,it has been one of the hotspots in researches.Mastering the key technologies of application compilation under the heterogeneous multi-core So C architecture is an important means to exert the performance of the architecture.Task scheduling is an important method for the compiler to maximize the parallelism of program execution and to improve the execution efficiency.This dissertation introduces the research status of the key technologies of heterogeneous multicore So C compilation,and researches on the main issues.This dissertation is focused on the key features in this architecture,including heterogeneity,NoC communication architecture,and memory constraints,and abstracts the computing system in problem into specific models.On this basis,for each system model,the corresponding scheduling algorithm is studied,so as to master the processing methods of three key system features in task scheduling,and finally the scheduling algorithm for the system model including all features is studied.The main work and achievements of this dissertation are as follows:(1)Aiming at heterogeneity,a list scheduling algorithm with quadratic time complexity for heterogeneous computing systems is proposed.In this algorithm,by introducing the backward prediction cost of tasks in the task prioritizing phase,a new improved prediction cost matrix is proposed and used in the task prioritizing phase.A better solution is obtained in the processor selection phase.(2)Aiming at the features of NoC communication structure and heterogeneity,a communication-aware and predictive list scheduling algorithm with quadratic time complexity is propose.A predictive approach is used in the task prioritizing and processor selection phase,and communication-aware approach of NoC architecture is applied in the processor selection phase.By this algorithm,better application scheduling results are obtained.(3)Aiming at the features of memory constraints and heterogeneity,a memoryconstraint-aware list scheduling algorithm is proposed.This algorithm has the features of predictability of the execution of subsequent tasks in scheduling and awareness of realtime capacity constraints of system memory.While maintaining the predictability of the two scheduling phases,by the method of coarse-grained memory timing generation,the feature of system memory capacity constraints real-time awareness is achieved in this algorithm.Proposed algorithm has better performance and has polynomial time complexity.(4)Considering the three major features of heterogeneous multi-core So C,a memoryconstraint NoC based heterogeneous multi-processor So C Model is established,and a list scheduling algorithm for this architecture is proposed.This algorithm combines the achievements of the previous three works,while being predictive,communication-aware,and memory-constraint-aware.Moreover,this algorithm is implemented under the framework of list scheduling,thus maintaining polynomial time complexity while obtaining better performance.By building the experimental platform,determining the comparison metrics and selecting the test set,a large number of random generated tasks and real-world tasks are loaded on the heterogeneous multi-core processor model.It is verified that the four algorithms proposed in this dissertation have a great improvement in scheduling length rate and speedup ratio.The above research results effectively solve the key task scheduling problem in the compilation technology of heterogeneous multi-core So Cs,exploits the performance potential of system architectural features,and alleviate the performance bottlenecks faced in the compilation of heterogeneous multi-core So C applications.An effective way is provided to improve the efficiency of this system.