Research On Modeling And Simulation Of Quantum Properties In Novel Nanoscale Semiconductor Logic Devices And Their Applications

Nowadays,the prosperity of Information Technology industry keeps posing great challenges to the improvement of the performance and integration of central processing unit chips,and the continuation of Moore’s Law is facing unprecedented pressure.In order to continue the Moore’s Law under the complementary metal-oxide-semiconductor（CMOS）technology,the size of nanoscale semiconductor transistors is approaching the physical limit of materials,causing significant quantum effects that seriously affect the performance of devices.Therefore,in recent years,the studies of quantum properties in materials and devices have become the focus in both academia and industry.In these studies,on the one hand researchers are striving to overcome the negative impact of quantum effects in traditional transistor logic elements.On the other hand,they have been making attempts to use the novel quantum properties of semiconductor materials,and explore some new development routes of logic computing beyond traditional CMOS technology.Therefore,solutions came into sight based on the spin and valley degrees of freedom in an electric charge,as well as quantum superposition principle.Focused on the novel nanoscale semiconductor logic devices of the above technical routes,this dissertation has carried out modeling,simulation and experimental research on their quantum properties,design and applications.The main contents and academic contributions of this dissertation are summarized as follows:1.For the new-generation FETs that suffer from significant quantum tunneling and quantum confinement effects at the nanoscale,research of modeling,simulation and analysis has been carried out.（1）A quantum transport simulation tool based on the real-space non-equilibrium Green’s function（NEGF）is independently developed,and the quantum confinement and quantum tunneling effects are carefully studied in ultra-thin-body MOSFETs with a channel length of 7 nm.The capacitance-voltage characteristics of the device are analyzed,based on which,the CMOS performance benchmarking is carried out,and the effects of parasitic components on short-channel devices are characterized.The basic physical mechanism of hole transport are clearly revealed.The effects of channel material,geometry,crystal orientation configuration,stress/strain and lattice scattering are deeply investigated for the overall performance of short-channel devices,which provides the theoretical guidance for device design and optimization.（2）An NEGF quantum transport method is established in mode-space with reduced order,and the hybrid quantum effects of nanosheet width and crystal orientation configuration are studied in stacked nanosheet gate-all-around MOSFETs at sub-5 nm technology nodes.An innovative statistical method is used to characterize the effect of process-induced nanosheet width deviations on the overall performance of stacked nanosheet FET array.By comparing with the Fin FET architecture under the same technology node,the crystal orientation configuration,number of stacks,channel and spacer widths in a nanosheet array are analyzed,with optimization scheme provided.（3）Considering the important effects of quantum confinement and crystal orientation configuration,the first accurate and comprehensive theoretical model of hole mobility in nanosheet FETs is rigorously established,which clearly depicts the physical portrait of momentum scatterings from phonons,charged impurities,and surface roughness.The low-field hole mobility in silicon and germanium nanosheet FETs is theoretically evaluated for different physical parameters,including device configuration,uniaxial stress,impurity concentration,interface roughness,and operating temperature.2.For the spin-FETs and quantum dots based on the 2D materials’quantum properties such as spintronics and valleytronics,（1）A spin transport simulation framework is established based on the dynamic spin Bloch equation,which accurately studies the spin relaxation and decoherence in 2D materials.Based on this,the first performance benchmarking of 2D-semiconductor spin-FET is carried out with respect to its MOSFET counterpart,which provides practical design guidance and implementation standards on the engineering of material,process,and device,for the realization of all-2D-material spin logic.（2）A density-functional-theory study of spintronic and valleytronic properties is conducted in 2D semiconductor materials,based on which,a tight-binding model accurate to the third-nearest-neighbor interaction is established for 2D-material quantum dots for the first time.Further,a quantum dot simulation tool is developed based on Schr（?）dinger-Poisson self-consistent solver.For electrostatic quantum dots of different 2D semiconductors,the self-consistent discrete energy levels are accurately simulated at cryogenic temperature.In-depth study is conducted for the effects of dot shape,size,defect atom and magnetic field modulation in 2D-semiconductor quantum dot system,providing an efficient simulation platform and theoretical guidance for the design and optimization of qubits in the system.3.Based on the architecture of new-generation nanosheet transistor and the design of2D-material spin transistor,a 2D-FET based on the graphene/WS₂/graphene lateral heterojunction is experimentally fabricated with success on its complete structure and good performance.Its physicochemical properties are comprehensively characterized and its electrical properties are systematically measured.This work accomplishes the practice of applying 2D materials to novel nanoscale logic devices,and verifies the possibility of realizing nanosheet-FETs and spin-FETs with 2D materials.