Research On Parallel Algorithms Using FPGA For Geometric Correction And Registration Of Remotely Sensed Imagery

Remote sensing(RS)images with high-precision geometric information have been widely used in the fields of resource survey,environment protection,disaster prevention and mitigation,major engineering construction and national defense construction,etc.,providing important data support for social sustainable development,economic construction and national major strategies in recent years.To extract accurate spatial information from RS images,it is necessary to project the original image into a georeferenced coordinate system for geometric processing.Therefore,geometric correction and registration have become the key technologies of geometric processing.However,the existing geometric correction technology of RS imagers need a lots of ground control points(GCPs)as the basis of data processing,and the acquisition process of GCPs is time-consuming and laborious.Therefore,an efficient method that can automatically select GCPs has become a hotspot and difficulty in the field of RS images.At the same time,the computation complexity of geometric correction is high.In order to improve the processing efficiency,many researches use platforms such as multi-core processors and graphic processing units(GPU)to perform parallel computing geometric correction and registration.However,it consumes a lot of power,which still cannot meet the tasks of on-board processing.Field programmable gate arrays(FPGA)has the characteristics of parallelism,hardware reuse and design flexibility.It has been successfully applied in computer vision,language processing,automatic driving and other related tasks.However,in order to realize high-speed computing based on FPGA,corresponding parallel algorithms need to be specially designed,and the current remote sensing image geometric correction and registration algorithms in the field of remote sensing do not have this ability.Therefore,this paper focuses on the parallel algorithm of geometric correction and registration based on FPGA for the task of on-board high-speed processing on the satellite.The main work is as follow:Aiming at the problem of time-consuming and labor-intensive of traditional geometric correction algorithms based on many GCPs,this paper proposes EORB(Enhanced Oriented FAST and Rotated BRIEF)parallel algorithm,which can automatically and quickly extract feature control points(FCPs)from the RS images,and select FCPs with good robustness to replaces GCPs.At the same time,in order to design a high-performance for FCPs detector within a small implementation area,a novel segmentation test algorithm,which is optimized based on the string searching algorithm,is utilized to implement the interest point detection in order to exploit bit-level parallelism.The proposed segment test method based on a string searching algorithm that searches a target string in long text.The experimental results show that the proposed segmentation test method based on string search can effectively replace the traditional decision tree method,which greatly reduce the complexity and improve the running speed of the EORB algorithm.Aiming at the high complexity of the traditional spatial feature point detection algorithm based on multi-scale Gaussian image pyramid,this paper proposes a feature point extraction based on box filter multi-scale space(called box space),using box filters with different sizes to replace Gaussian multi-scale space.The integral image technology is used to calculate the response of box filters with different sizes in parallel in a constant time,regardless of the box filter sizes.The word length reduction method is proposed to reduce the word length of the memory and the combined pipeline,serial and parallel methods are adopted to effectively trade-offs among accuracy,performance,and energy of an FPGA.Aiming at the low efficiency of geometric correction due to the complexity and a large number of inverse matrix operations in the construction of polynomial geometric correction model,this paper proposes a block LU parallel decomposition method(B-LUPD)to realize the matrix inversion operation,which speedup the computation and reduce the consumption of hardware resource.At last,the combined parallel polynomial model with the optimized parallel bilinear interpolation algorithm or the parallel cubic convolution interpolation algorithm with a parameter,two types of real-time geometric correction systems based on FPGA are designed.The experiments show that the root mean square errors(RMSE_x,RMSE_y,andRMSE)are less than one pixel,and the running speed is about 8 times than that of PC.In order to solve the problem of slow speed in the registration process of RS image,a parallel combined speed up robot features(SURF)and binary robust independent elementary(BRIEF)algorithms based on FPGA are proposed.A reconfigurable multi-scale space cache memory is proposed with row-based stream processing(RBSP)mode,which is a specific memory architecture for data accessing of integral image and integral histogram.RBSP technology is implemented the separable convolution of box filters with r-lines buffer cores,which can be read image pixels in parallel and quickly detect feature points on the FPGA platform.Experiments show that the running time of the integral image unit,SURF detection unit,BRIEF descriptor unit and BRIEF matching unit are 2.62us,2.6ms,2.48us and 15.56us respectively.The total running time is about 2.62ms and the frame rate is 380 frame per second(fps)at 100 MHz,which satisfies the real-time and low-power requirements of embedded devices.