| A press pack-injection enhanced gate transistor(PP-IEGT)combines the advantage of PP package that allows more chips in parallel and short circuit failure with the IEGT chip’s advantages of lower on-state loss.It has been applied in many flexible high voltage direct current projects.However,as the number increase of the parallel chips,the problems such as packaging parasitic effect and clamping deviation become more serious,making the distribution of electric field,thermal field,and stress field among chips more complex.Ⅳ,and the whole device is exposed to the short circuit failure.Thus,it is of great significance to carry out studies on the electro-thermal-stress characterizations of PP-IEGT parallel chips,such as the influence factor of inside and outside of the package on current sharing,the relationship between external clamping variables and stress distribution of chips,and the variance of contact degradation of parallel branches,which is beneficial to explore the failure process and optimizing device.In this paper,a lumped-charge model of IEGT single chip is constructed.The influence of parasitic parameters,clamping force,and temperature on the electrical parameter distribution uniformity of PP-IEGT parallel chip is comprehensively quantified.The effect of the external clamping conditions and the internal contact parameter on the thermalstress distribution among chips are studied to determine the weak region within the package.A three-parameter electrical contact degradation model is proposed.The main research contents are as follows.Study on lumped charge model of single IEGT chip considering the characteristics of IEGT carrier characteristic.The carrier current equations between nodes and the boundary conditions are constructed for the traditional IGBT region and the region below the floating Player,respectively.And,the relevant parameters of the model are extracted.As for the PP package,the relationship between carrier mobility and the clamping force is described by using the piezoresistive model to improve the applicability of IEGT model.The experimental results verify that the model could accurately represent the static and transient characteristics of IEGT.Based on the multi-parameter synchronous test platform,it is verified that the decrease of clamping force and the increase of temperature prolong the switching time,and increase the switching energy.In addition,the output curves at different temperatures intersect at 1.9A and2.3V,which makes the dependence of saturation drop on temperature can be ignored.Study on current sharing of parallel branches considering the multi-chip parallel structure of PP-IEGT.Firstly,from the perspective of the package structure,the parasitic inductance of components is extracted based on Q3 D simulation and the frequency domain impedance.The accuracy of the extraction of the parasitic inductance is verified with the S-parameter port method.The results show that the driving parasitic inductance and the mutual inductance of the pillars are the main factors causing the current imbalance.Furthermore,combined with IEGT lumped charge model,the effects of parasitic inductance,clamping force,and temperature on current sharing are compared.The results show that the current imbalance caused by the parasitic effect is more obvious under the condition of too small clamping force and too high junction temperature.The current density distribution among chips has obvious skin effects and adjacent effects.Increasing the chips’ gap can effectively weaken the parasitic mutual inductance coefficient and improve the uniformity of current density distribution.Study on distribution uniformity of thermal-stress parameter of parallel branches considering the multi-chip parallel structure of PP-IEGT.By Simplorer software,the power loss of each branch calculated above is loaded on the corresponding chip as heat source load.A three-dimensional thermal network model including the thermal couple effect is proposed to achieve the rapid prediction of junction temperature.PP-IEGT and heat sink series model is constructed to reveal the influence of external parameters and internal structure on the thermal expansion warping of collector and the stress distribution among parallel chips.The optimal clamping size and chips’ gap are optimized.Compared with the initial conditions,the temperature difference and stress difference between chips can be significantly decreased with the increase of the clamping radius,which plays a positive role in improving the uniformity of stress distribution between chips.Study on the difference of electrical contact degradation of parallel branches considering the characteristic of the press pack package.By using finite element analysis,power cycling test,and microscopic characterization,the electrical contact degradation caused by thermal expansion is studied.The results show that the chip’s corner region displays a higher fretting wear degree,and the breakdown points are all located in these regions.The contact resistance of the edge branch increases more than that of the central branch.Based on the degradation state,the lumped charge model and the contact settings of the co-simulation are updated.The updated results illustrate that the distribution uniformity of electro-thermal-stress parameters among chips is seriously reduced,and the edge branch faces a greater failure risk.Moreover,based on the grey theory,the three-parameter Weibull model of the edge branch is constructed.The failure rate of PP-IEGT increases with time,and the failure type is dissipation failure.In this paper,the quantitative relationship between the distribution uniformity of electrothermal-stress parameters among multichip and the related influencing factors is explored by theoretical analysis,numerical simulation,and experimental methods.And then,the electrical contact degradation discrepancy of parallel branches is quantified.The results of this paper can provide theoretical and practical support for the optimization and improvement of parameter distribution uniformity between PP-IEGT chips,and also offer a reference basis for the failure analysis of related PP packaging devices. |
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