Research On Wafer-Level Packaging For High-Precision Silicon Based Accelerometer Applications

Silicon based MEMS accelerometers are widely used in consumer electronics,inertial navigation and earth resource exploration.Many research institutions of China and overseas have conducted comprehensive researches on this topic and proposed different types of MEMS accelerometers,among which capacitive MEMS accelerometers have experienced a rapid development.In the design,processing,reliability,testing and using of an accelerometer,the packaging process is playing a key role in realizing high performance.MEMS devices often require unique packaging methods due to the complexities in their structure and operation,thus unique way of analysis is needed to determine the packaging method for certain types of device.This research focus on the wafer-level packaging technology for high-precision silicon based accelerometers.Starting from the working principle of the accelerometer,requirements of the wafer-level packaging are investigated,including the plate spacing,the control of the in-plane offset and the packaging structure.Then the packaging scheme is designed.An 8μm plate spacing,1.18μm spacing difference,5μm in-plane offset and 0.1mrad in-plane rotation are designed.At the same time,the encapsulation ring structure and cut channel structure are needed for providing protections and electrical connections.By analyzing the thermal stress of the bonding process,a new three-layer bonding method which only contains one temperature process is proposed.The lower cover and the spring structure are pre-bonded through a silicon-silicon bonding process,and then the pre-bonded two-layer structure is bonded with the upper cover through a gold-gold comprehension bonding process,simultaneously an annealing process is provided for the pre-bonded structure.Next,the compatibility of the single-step wafer-level packaging is studied.Typical single-step processes include the direct bonding process,the comprehension bonding process,the signal extraction through hole process and the wire bonding process.Process parameters are figured out.The process incompatibility problem in part of the packaging process is solved.However,our result does not meet the requirements due to the unstable gold electroplating process on the upper cover.The initial design of the wafer-level packaging method has been improved,method for the plate spacing control has been realized by a wet etching grooves over the top cover.The feasibility of the new protocol is verified and used in the fabrication,packaging and chipping of the accelerometer.The survival rate of devices cut-off the silicon chip was 80%,the hermeticity of the device reached（4.0±1.6）×10^-10atm.cc/s,and the bonding strength was8.6±0.9J/m²,which indicates the high quality of packaging.Then the four-point roll test under gravity is carried out on the wafer-level packaged accelerometer to calibrate the scale factor,the scale factor of the accelerometer is measured to be 306.5±12.5m V/g,and the consistency m of the scale factor of the accelerometer in different areas on the wafer was greater than 0.91,which shows a good consistency.The wafer-level packaging of the high-precision silicon based accelerometer was initially realized,and the accelerometer functions normally.The impact-proof bump in accelerometer packaging is also studied in this research.By controlling volumes of the solder and the area of the solder pad,the 3D solder bump of different heights could be obtained through a one-step electroplating and reflux process.Experimental results demonstrate the linear relationship between the height of solder bump and the ratio of the plating window and the pad area.The impact prevention function of the solder bumps is then verified.Solder bumps produce deformation to absorb the impact energy.Experimental results show that the structure can resist an impact from 780g to 1170g,offering good impact prevention.In summary,the requirement analysis,scheme design,fabrication processes development and scheme optimization on the wafer-level packaging of the high-precision silicon based accelerometer have been studied,as well as the preparation and testing of an accelerometer for proof-of-concept.Results show that the wafer-level packaging of the high-precision silicon based accelerometer has been realized with proper functions and good performance.